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1 for more information www.linear.com/LTC2312-14 typical a pplica t ion fea t ures descrip t ion 14-bit, 500ksps serial sampling adc in tsot the lt c ? 2312-14 is a 14-bit, 500 ksps, serial sampling a/d converter that draws only 3.2 ma from a single 3v or 5 v supply. the LTC2312-14 contains an integrated low drift reference and reference buffer providing a low cost, high performance (20 ppm/c maximum) and space saving solution. the LTC2312-14 achieves outstanding ac performance of 77 db sinad and C85db thd while sampling at 500 ksps. the extremely high sample rate-to- power ratio makes the LTC2312-14 ideal for compact, low power, high speed systems. the supply current decreases at lower sampling rates as the device automatically enters nap mode after conversions. the LTC2312-14 has a high speed spi-compatible serial interface that supports 1.8v, 2.5v, 3 v and 5 v logic. the fast 500 ksps throughput with no-cycle latency makes the LTC2312-14 ideally suited for a wide variety of high speed applications. complete 14-/12-bit pin-compatible sar adc family 500ksps 2.5msps 4.5msps 5msps 14-bit LTC2312-14 ltc2313-14 ltc2314-14 12-bit ltc2312-12 ltc2313-12 ltc2315-12 power 3v/5v 9 mw/15mw 14mw/25mw 18mw/31mw 19mw/32mw a pplica t ions n 500ksps throughput rate n no cycle latency n guaranteed 14-bit no missing codes n single 3v or 5v supply n low noise: 77.5db snr n low power: 9mw at 500ksps and 3v supply n low drift (20ppm/c maximum) 2.048v or 4.096v internal reference n sleep mode with < 1a typical supply current n nap mode with quick wake-up < 1 conversion n separate 1.8v to 5v digital i/o supply n high speed spi-compatible serial i/o n guaranteed operation from C 40c to 125c n 8-lead tsot-23 package n communication systems n high speed data acquisition n handheld terminal interface n medical imaging n uninterrupted power supplies n battery operated systems n automotive l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 5v supply, internal reference, 500ksps, 14-bit sampling adc 16k point fft , f s = 500ksps, f in = 259khz 231214 ta01b input frequency (khz) amplitude (dbfs) 0 200 250 10050 150 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 v dd = 5v snr = 77.5dbfs sinad = 77dbfs thd = ?85db sfdr = 88db serial data link to asic, pld, mpu, dsp or shift registers analog input 0v to 4.096v 5v 2.2f 2.2f 2.2f 231214 ta01 gnd v dd ref a in ov dd sck conv sdo LTC2312-14 digital output supply 1.8v to 5v 231214f ltc 2312-14
2 for more information www.linear.com/LTC2312-14 p in c on f igura t ion a bsolu t e maxi m u m r a t ings supply voltage (v dd , ov dd ) ....................................... 6v ref erence ( ref ) and analog input (a in ) voltage ( note 3) ...................................... (C 0.3 v) to (v dd + 0.3 v) digital input voltage ( note 3) ... (C 0.3 v) to ( ov dd + 0.3 v) digital output voltage ............. (C 0.3 v) to ( ov dd + 0.3 v) power dissipation ............................................... 10 0 mw operating temperature range ltc 2 312 c ................................................ 0 c to 70 c ltc 2 312 i .............................................. C4 0 c to 85 c ltc 2 312 h .......................................... C 40 c to 125 c storage temperature range .................. C 65 c to 150 c lead temperature range ( soldering , 10 sec ) ........ 30 0 c (notes 1, 2) 1 2 3 4 8 7 6 5 top view ts8 package 8-lead plastic tsot-23 conv sck sdo ov dd v dd ref gnd a in t jmax = 150c, ja = 195c/w o r d er i n f or m a t ion lead free finish tape and reel (mini) tape and reel part marking* package description temperature range ltc2312cts8-14#trmpbf ltc2312cts8-14#trpbf ltfzk 8-lead plastic tsot-23 0c to 70c ltc2312its8-14#trmpbf ltc2312its8-14#trpbf ltfzk 8-lead plastic tsot-23 C40?c to 85?c ltc2312hts8-14#trmpbf ltc2312hts8-14#trpbf ltfzk 8-lead plastic tsot-23 C40?c to 125?c trm = 500 pieces. *temperature grades are identified by a label on the shipping container. consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 231214f ltc 2312-14
3 for more information www.linear.com/LTC2312-14 e lec t rical c harac t eris t ics c onver t er c harac t eris t ics dyna m ic a ccuracy symbol parameter conditions min typ max units v ain absolute input range l C0.05 v dd + 0.05 v v in input voltage range (note 11) l 0 v ref v i in analog input dc leakage current l C1 1 a c in analog input capacitance sample mode hold mode 13 3 pf pf symbol parameter conditions min typ max units resolution l 14 bits no missing codes l 14 bits transition noise (note 6) 0.7 lsb rms inl integral linearity error v dd = 5v (note 5) v dd = 3v (note 5) l l C3.75 C4 1 1.5 3.75 4 lsb lsb dnl differential linearity error v dd = 5v v dd = 3v l l C0.99 C0.99 0.3 0.4 0.99 0.99 lsb lsb offset error v dd = 5v v dd = 3v l l C9 C18 2 4 9 18 lsb lsb full -scale error v dd = 5v v dd = 3v l l C18 C34 5 7 18 34 lsb lsb t otal unadjusted error v dd = 5v v dd = 3v l l C22 C38 6 8 22 38 lsb lsb symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio f in = 20khz, v dd = 5v f in = 20khz, v dd = 3v l l 72.5 69 77 72.6 db db snr signal -to-noise ratio f in = 20khz, v dd = 5v f in = 20khz, v dd = 3v l l 73.5 69.5 77.5 73 db db thd t otal harmonic distortion first 5 harmonics f in = 20khz, v dd = 5v f in = 20khz, v dd = 3v l l C85 C85 C76 C76 db db sfdr spurious free dynamic range f in = 20khz, v dd = 5v f in = 20khz, v dd = 3v l l 78 76 88 88 db db imd intermodulation distortion 2nd order t erms 3rd order terms f in1 = 53khz, f in2 = 58khz, a in1 , a in2 = C7dbfs C80 C92 dbc dbc full power bandwidth at 3db at 0.1db 130 20 mhz mhz C3db input linear bandwidth sinad 74db 5 mhz t ap aperture delay 1 ns t jitter aperture jitter 10 ps rms the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and a in = C1dbfs. (note 4) 231214f ltc 2312-14
4 for more information www.linear.com/LTC2312-14 r e f erence i npu t / o u t pu t p ower r equire m en t s digi t al i npu t s an d digi t al o u t pu t s symbol parameter conditions min typ max units v ref v ref output voltage 2.7v v dd 3.6v 4.75 v dd 5.25v l l 2.040 4.080 2.048 4.096 2.056 4.112 v v v ref temperature coefficient l 7 20 ppm/c v ref output resistance normal operation, i load = 0ma to 5ma overdrive condition (v refin v refout + 50mv) 1 52 k v ref line regulation 2.7v v dd 3.6v 4.75 v dd 5.25v 0.4 0.2 mv/v mv/v v ref 2.048v/4.096v supply threshold 4.15 v v ref 2.048v/4.096v supply threshold hysteresis 150 mv v ref input voltage range (external reference input) 2.7 v v dd 3.6v 4.75 v dd 5.25v l l v ref + 50mv v ref + 50mv v dd 4.3 v v symbol parameter conditions min typ max units v dd supply voltage 3v operational range 5v operational range l l 2.7 4.75 3 5 3.6 5.25 v v ov dd digital output supply voltage l 1.71 5.25 v i total = i vdd + i ovdd supply current, static mode operational mode nap mode sleep mode conv = 0v, sck = 0v l l l 3.4 3.2 2 0.2 4.3 4 5 ma ma ma a p d power dissipation, static mode operational mode nap mode sleep mode conv = 0v, sck = 0v l l l 17 16 10 1 21.5 20 25 mw mw mw w symbol parameter conditions min typ max units v ih high level input voltage l 0.8 ? ov dd v v il low level input voltage l 0.2 ? ov dd v i in digital input current v in = 0v to ov dd l C10 10 a c in digital input capacitance 5 pf v oh high level output voltage i o = C500a (source) l ov dd C0.2 v v ol low level output voltage i o = 500a (sink) l 0.2 v i oz hi-z output leakage current v out = 0v to ov dd , conv = high l C10 10 a c oz hi-z output capacitance conv = high 4 pf i source output source current v out = 0v, ov dd = 1.8v C20 ma i sink output sink current v out = ov dd = 1.8v 20 ma the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) 231214f ltc 2312-14
5 for more information www.linear.com/LTC2312-14 a d c ti m ing c harac t eris t ics symbol parameter conditions min typ max units f sample(max) maximum sampling frequency (notes 7, 8) l 500 khz f sck shift clock frequency (notes 7, 8) l 20 mhz t sck shift clock period l 50 ns t throughput minimum throughput time, t acq + t conv l 2000 ns t conv conversion time l 1300 ns t acq acquisition time l 700 ns t 1 minimum conv pulse width (note 7), valid for nap and sleep modes only l 10 ns t 2 sck setup time after conv (note 7) l 10 ns t 3 sdo enable time after conv (notes 7, 8) l 10 ns t 4 sdo data valid access time after sck (notes 7, 8, 9) l 11 ns t 5 sck low time l 10 ns t 6 sck high time l 10 ns t 7 sdo data valid hold time after sck (notes 7, 8, 9) l 1 ns t 8 sdo into hi-z state time after conv (notes 7, 8, 10) l 3 10 ns t 9 conv quiet time after 14th sck (note 7) l 15 ns t wake _ nap power-up time from nap mode see nap mode section 50 ns t wake _ sleep power-up time from sleep mode see sleep mode section 1.1 ms the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 4) note 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2 . all voltage values are with respect to ground. note 3. when these pin voltages are taken below ground or above v dd (a in , ref) or ov dd (sck, conv, sdo) they will be clamped by internal diodes. this product can handle input currents up to 100ma below ground or above v dd or ov dd without latch-up. note 4. v dd = 5v, ov dd = 2.5v, f smpl = 500khz, f sck = 20mhz, a in = C1dbfs and internal reference unless otherwise noted. note 5. integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 6. typical rms noise at code transitions. note 7. parameter tested and guaranteed at ov dd = 2.5v. all input signals are specified with t r = t f = 1ns (10% to 90% of ov dd ) and timed from a voltage level of ov dd /2. note 8. all timing specifications given are with a 10pf capacitance load. load capacitances greater than this will require a digital buffer. note 9. the time required for the output to cross the v oh or v ol voltage. note 10. guaranteed by design, not subject to test. note 11. recommended operating conditions. 231214f ltc 2312-14
6 for more information www.linear.com/LTC2312-14 typical p er f or m ance c harac t eris t ics 16k point fft , f s = 500ksps f in = 259khz snr, sinad vs input frequency (100khz to 1.2mhz) thd, harmonics vs input frequency (100khz to 1.2mhz) thd, harmonics vs input frequency (100khz to 1.2mhz) snr, sinad vs temperature, f in = 259khz thd, harmonics vs temperature , f in = 259khz integral nonlinearity vs output code differential nonlinearity vs output code dc histogram near mid-scale (code 8192) t a = 25c , v dd = 5v , ov dd = 2.5v , f smpl = 500ksps, unless otherwise noted. output code 0 ?2.0 ?1.0 ?1.5 inl (lsb) ?0.5 0.5 0.0 1.0 1.5 2.0 4096 8192 12288 16384 231214 g01 output code 0 ?1.00 ?0.75 ?0.50 dnl (lsb) ?0.25 0.25 0.00 0.50 0.75 1.00 4096 8192 12288 16384 231214 g02 temperature (c) ?55 ?35 ?100 ?95 thd, harmonics (db) ?90 ?85 ?80 ?75 ?15 5 25 45 65 85 105 125 231214 g09 thd 3rd 2nd v dd = 3v input frequency (khz) 0 72 73 snr, sinad (dbfs) 75 74 76 77 78 500 250 750 1000 1250 231214 g05 sinad snr sinad snr v dd = 5v v dd = 3v input frequency (khz) 0 ?105 ?95 ?100 thd, harmonics (db) ?90 ?85 ?80 ?75 500 250 750 1000 1250 231214 g06 thd 2nd 3rd r in /c in = 50/47pf f s = 500ksps v dd = 5v input frequency (khz) 0 ?105 ?95 ?100 thd, harmonics (db) ?90 ?85 ?80 ?75 500 250 750 1000 1250 231214 g07 thd 2nd 3rd r in /c in = 50/47pf f s = 500ksps v dd = 3v temperature (c) ?55 ?35 71 74 73 72 snr, sinad (dbfs) 75 76 78 77 79 ?15 5 25 45 65 85 105 125 231214 g08 snr snr sinad sinad v dd = 5v v dd = 3v 231214 g04 input frequency (khz) amplitude (dbfs) 0 200 250 10050 150 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 v dd = 5v snr = 77.5dbfs sinad = 77dbfs thd = ?85db sfdr = 88db 5000 2000 8195 0 7000 counts 8199 3000 6000 8200 231214 g03 8194 code 8196 4000 8198 231214f = 0.7 8197 ltc 2312-14 1000
7 for more information www.linear.com/LTC2312-14 typical p er f or m ance c harac t eris t ics supply current vs temperature shutdown current vs temperature supply current vs sample rate reference current vs reference voltage full-scale error vs temperature offset error vs temperature snr, sinad vs reference voltage f in = 259khz thd, harmonics vs temperature, f in = 259khz t a = 25c , v dd = 5v , ov dd = 2.5v , f smpl = 500ksps, unless otherwise noted. temperature (c) ?55 ?1 offset error (lsb) 0 ?0.5 0.5 1 ?35 ?15 5 4525 8565 105 125 231214 g14 temperature (c) ?55 0 shutdown current (a) 0.25 0.5 1 0.75 ?35 ?15 5 4525 8565 105 125 231214 g16 v dd = 5v v dd = 3v i vdd + i ovdd reference voltage (v) 2 72 snr, sinad (dbfs) 75 74 73 77 76 79 78 2.5 3 3.5 4 4.5 231214 g11 snr snr sinad sinad v dd = 3.6v operation not allowed v dd = 5v temperature (c) ?55 ?4 full-scale error (lsb) ?1 0 ?3 ?2 1 2 3 4 ?35 ?15 5 4525 8565 105 125 231214 g13 temperature (c) ?55 supply current (ma) ?35 ?15 5 4525 8565 105 125 231214 g15 2.5 2.9 2.7 2.6 3.1 3.5 3.3 2.8 3.0 3.4 3.2 v dd = 5v v dd = 3v temperature (c) ?55 ?35 ?110 ?100 ?105 ?95 thd, harmonics (db) ?90 ?85 ?80 ?75 ?15 5 25 45 65 85 105 125 231214 g10 thd 3rd 2nd v dd = 5v reference voltage (v) 2 100 reference current (a) 150 200 2.5 3 3.5 4 4.5 231314 g12 v dd = 3.6v operation not allowed v dd = 5v sample rate (khz) 0 0 supply current (ma) 1.0 2.0 2.5 1.5 0.5 3.5 3.0 100 200 300 400 500 231214 g17 i tot i vdd v dd = 5v ov dd = 2.5v i ovdd 231214f ltc 2312-14
8 for more information www.linear.com/LTC2312-14 t a = 25c , v dd = 5v , ov dd = 2.5v , f smpl = 500ksps, unless otherwise noted. p in func t ions v dd (pin 1): power supply. the ranges of v dd are 2.7v to 3.6 v and 4.75 v to 5.25 v. bypass v dd to gnd with a 2.2f ceramic chip capacitor. ref (pin 2): reference input/ output. the ref pin volt - age defines the input span of the adc, 0 v to v ref . by default, ref is an output pin and produces a reference voltage v ref of either 2.048 v or 4.096 v depending on v dd ( see table 2). bypass to gnd with a 2.2 f , low esr, high quality ceramic chip capacitor. the ref pin may be overdriven with a voltage at least 50mv higher than the internal reference voltage output. gnd (pin 3): ground. the gnd pin must be tied directly to a solid ground plane. a in ( pin 4): analog input. a in is a single-ended input with respect to gnd with a range from 0v to v ref . ov dd (pin 5): i/o interface digital power. the ov dd range is 1.71 v to 5.25 v. this supply is nominally set to the same supply as the host interface (1.8v, 2.5v, 3.3 v or 5v). bypass to gnd with a 2.2 f ceramic chip capacitor. sdo (pin 6): serial data output. the a/d conversion result is shifted out on sdo as a serial data stream with the msb first through the lsb last. the data stream consists of 14 bits of conversion data followed by trailing zeros. there is no cycle latency. logic levels are determined by ov dd . sck (pin 7): serial data clock input. the sck serial clock synchronizes the serial data transfer. sdo data transitions on the falling edge of sck. logic levels are determined by ov dd . conv (pin 8): convert input. this active high signal starts a conversion on the rising edge. the conversion is timed via an internal oscillator. the device automatically powers down following the conversion process. the sdo pin is in high impedance when conv is a logic high. bringing conv low enables the sdo pin and outputs the msb. subsequent bits of the conversion data are read out seri - ally on the falling edge of sck. a logic low on conv also places the sample- and- hold into sample mode. logic levels are determined by ov dd . output supply current (i ovdd ) vs output supply voltage (ov dd ) supply current (i vdd ) vs supply voltage (v dd ) typical p er f or m ance c harac t eris t ics output supply voltage (v) 1.8 0 output supply current (ma) 0.1 0.2 0.5 0.4 0.3 2.62.2 3.43.0 3.8 4.2 4.6 5.0 231214 g19 supply voltage (v) 2.6 2.50 supply current (ma) 2.75 3.00 3.25 3.50 2.9 3.83.53.2 4.1 4.74.4 5.35.0 231214 g18 operation not allowed 231214f ltc 2312-14
9 for more information www.linear.com/LTC2312-14 ti m ing diagra m s b lock diagra m 231214 bd 4 ? + s/h 2.5v ldo 2/4 1.024v bandgap timing logic 1 6 7 8 three-state serial output port 14-bit sar adc 2 3 a in ref v dd ov dd 2.2f gnd analog input range 0v to v ref analog supply 3v or 5v i/o interface supply range 1.8v to 5v 5 2.2f 2.2f sdo sck conv ts8 package all capacitors unless noted are high quality, ceramic chip type 231214 td04 231214 td03 231214 td02 231214 td01 hi-z conv ov dd /2 sdo t 8 ov dd /2 t 7 figure 1. sdo enabled after conv figure 3. sdo data valid hold after sck figure 2. sdo into hi-z after conv figure 4. sdo data valid access after sck v oh v ol sck sdo hi-z msb conv ov dd /2 sdo t 3 v oh v ol sck ov dd /2 sdo t 4 v oh v ol 231214f ltc 2312-14
10 for more information www.linear.com/LTC2312-14 a pplica t ions i n f or m a t ion overview the LTC2312-14 is a low noise, high speed , 14- bit succes- sive approximation register ( sar) adc. the LTC2312-14 operates from a single 3 v or 5 v supply and provides a low drift (20 ppm/c maximum), internal reference and refer - ence buffer. the internal reference buffer is automatically configured with a 2.048 v span in low supply range (2.7v to 3.6 v) and with a 4.096 v span in the high supply range (4.75v to 5.25 v). the LTC2312-14 samples at a 500ksps rate and supports a 20 mhz serial data read clock. the LTC2312-14 achieves excellent dynamic performance (77db sinad , 85 db thd) while dissipating only 15mw from a 5 v supply up to the 500 ksps conversion rate. the LTC2312-14 outputs the conversion data with no cycle latency onto the sdo pin. the sdo pin output logic lev - els are supplied by the dedicated ov dd supply pin which has a wide supply range (1.71 v to 5.25 v) allowing the LTC2312-14 to communicate with 1.8v, 2.5v, 3 v or 5v systems. the LTC2312-14 automatically switches to nap mode following the conversion process to save power. the device also provides a sleep power-down mode through serial interface control to reduce power dissipation during long inactive periods. serial interface the LTC2312-14 communicates with microcontrollers, dsps and other external circuitry via a 3- wire interface. a rising conv edge starts the conversion process which is timed via an internal oscillator. following the conver - sion process the device automatically switches to nap mode to save power as shown in figure 7. this feature saves considerable power for the LTC2312-14 operating at lower sampling rates. as shown in figures 5 and 6, it is recommended to hold sck static low or high during t conv . note that conv must be held high for the entire minimum conversion time ( t conv ). a falling conv edge enables sdo and outputs the msb. subsequent sck falling edges clock out the remaining data as shown in figures 5 and 6. data is serially output msb first through lsb last, followed by trailing zeros if further sck falling edges are applied. serial data output (sdo) the sdo output is always forced into the high imped - ance state while conv is high. the falling edge of conv enables sdo and also places the sample and hold into sample mode. the a/d conversion result is shifted out on the sdo pin as a serial data stream with the msb first. the msb is output on sdo on the falling edge of conv. delay t 3 is the data valid access time for the msb. the following 13 bits of conversion data are shifted out on sdo on the falling edge of sck. delay t 4 is the data valid access time for output data shifted out on the falling edge of sck. there is no data latency. subsequent falling sck edges applied after the lsb is output will output zeros indefinitely on the sdo pin. the output swing on the sdo pin is controlled by the ov dd pin voltage and supports a wide operating range from 1.71 v to 5.25 v independent of the v dd pin voltage. power considerations the LTC2312-14 provides two sets of power supply pins : the analog power supply (v dd ) and the digital input/output interface power supply (ov dd ). the flexible ov dd supply allows the LTC2312-14 to communicate with any digital logic operating between 1.8 v and 5 v, including 2.5 v and 3.3v systems. entering nap/sleep mode pulsing conv two times and holding sck static places the LTC2312-14 into nap mode. pulsing conv four times and holding sck static places the LTC2312-14 into sleep mode. in sleep mode, all bias cir cuitry is shut down, including the internal bandgap and reference buffer, and only leakage currents remain (0.2 a typical). because the reference buffer is externally bypassed with a large capacitor (2.2f ), the LTC2312-14 requires a significant wait time (1.1 ms) to recharge this capacitance before an accurate conversion can be made. in contrast, nap mode does not power down the internal bandgap or reference buffer allowing for a fast wake- up and accurate conversion within one conversion clock cycle. supply current during nap mode is nominally 2 ma. 231214f ltc 2312-14
11 for more information www.linear.com/LTC2312-14 figure 6. LTC2312-14 serial interface timing diagram (sck high during t conv ) figure 7. LTC2312-14 nap mode power-down following conversion for t conv > t conv-min a pplica t ions i n f or m a t ion figure 5. LTC2312-14 serial interface timing diagram (sck low during t conv ) t throughput t acq t conv-min t acq-min = 13.5 ? t sck + t 2 + t 9 1413 124321 conv sck sdo hi-z state 231214 f05 t 6 t 2 (msb) b1 b0 0 b10 b11 b12 b13 t 5 t 4 t 7 t 3 t 8 t 9 t throughput t acq t conv-min t acq-min = 13.5 ? t sck + t 2 + t 9 14 13 4321 conv sck sdo hi-z state 231214 f06 t 6 t 2 (msb) b1 b0 0 b10 b11 b12 b13 t 5 t 4 t 7 t 3 t 8 t 9 t conv > t conv-min t acq t conv-min nap mode conv sck sdo hi-z state convert power-down 231214 f07 (msb) b12 b13 t 3 t 9 t 2 t 8 231214f ltc 2312-14
12 for more information www.linear.com/LTC2312-14 a pplica t ions i n f or m a t ion exiting nap/sleep mode waking up the LTC2312-14 from either nap or sleep mode, as shown in figures 8 and 9, requires sck to be pulsed one time. a conversion may be started immediately fol - lowing nap mode as shown in figure 8. a period of time allowing the reference voltage to recover must follow waking up from sleep mode as shown in figure 9. the wait period required before initiating a conversion for the recommended value of c ref of 2.2f is 1.1ms. power supply sequencing the LTC2312-14 does not have any specific power sup - ply sequencing requirements. care should be taken to observe the maximum voltage relationships described in the absolute maximum ratings section. single-ended analog input drive the analog input of the LTC2312-14 is easy to drive. the input draws only one small current spike while charging the sample-and-hold capacitor following the falling edge of conv. during the conversion, the analog input draws only a small leakage current. if the source impedance of the driving circuit is low, then the input of the LTC2312-14 can be driven directly. as the source impedance increases, so will the acquisition time. for minimum acquisition time figure 8. LTC2312-14 entering/exiting nap mode figure 9. LTC2312-14 entering/exiting sleep mode with high source impedance, a buffer amplifier should be used. the main requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion starts. settling time must be less than t acq-min (700 ns) for full performance at the maximum throughput rate. while choosing an input ampli - fier, also keep in mind the amount of noise and harmonic distortion the amplifier contributes. choosing an input amplifier choosing an input amplifier is easy if a few requirements are taken into consideration. first, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (<50) at the closed-loop bandwidth frequency. for example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 50 mhz, then the output impedance at 50 mhz must be less than 50. the second requirement is that the closed-loop bandwidth must be greater than 50 mhz to ensure adequate small signal settling for full throughput rate. if slower op amps are used, more time for settling can be provided by in - creasing the time between conversions. the best choice for an op amp to drive the LTC2312-14 will depend on the application. generally, applications fall into two categories: ac applications where dynamic specifications are most conv sck z 1 2 z sdo hi-z state 231214 f08 nap mode hold static high or low hold static high or low start t acq t 1 conv sck 1 2 z z 3 4 sdo hi-z state 231214 f09 nap mode sleep mode hold static high or low start t acq v ref recovery t wait 231214f ltc 2312-14
13 for more information www.linear.com/LTC2312-14 a pplica t ions i n f or m a t ion critical and time domain applications where dc accuracy and settling time are most critical. the following list is a summary of the op amps that are suitable for driving the LTC2312-14. ( more detailed information is available on the linear technology website at www.linear.com.) lt6230: 215 mhz gbwp, C80 dbc distortion at 1mhz, unity-gain stable, rail-to-rail input and output , 3.5ma/ amplifier, 1.1nv/ hz. lt6200 : 165 mhz gbwp , C85 dbc distortion at 1 mhz, unity - gain stable, r-r in and out , 15ma/amplifier, 0.95nv/ hz. lt1818/1819: 400mhz gbwp, C85dbc distortion at 5 mhz, unity-gain stable , 9 ma/amplifier, single/dual voltage mode operational amplifier. input drive circuits the analog input of the LTC2312-14 is designed to be driven single- ended with respect to gnd. a low impedance source can directly drive the high impedance analog input of the LTC2312-14 without gain error. a high impedance source should be buffered to minimize settling time during acquisi - tion and to optimize the distortion performance of the adc. for best performance, a buffer amplifier should be used to drive the analog input of the LTC2312-14. the amplifier provides low output impedance to allow for fast settling of the analog signal during the acquisition phase. it also provides isolation between the signal source and the adc inputs which draw a small current spike during acquisition. input filtering the noise and distortion of the buffer amplifier and other circuitry must be considered since they add to the adc noise and distortion. noisy input circuitry should be filtered prior to the analog inputs to minimize noise. a simple 1-pole rc filter is sufficient for many applications. large filter rc time constants slow down the settling at the analog inputs. it is important that the overall rc time constants be short enough to allow the analog inputs to completely settle to >14-bit resolution within the minimum acquisition time (t acq-min ) of 700ns. a simple 1- pole rc filter is sufficient for many applications . for example, figure 10 shows a recommended single- ended buffered drive circuit using the lt1818 in unity gain mode. the 470 pf capacitor from a in to ground and 50 source resistor limits the input bandwidth to 7mhz. the 470 pf capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the lt1818 from sampling glitch kick-back. the 50 source resistor is used to help stabilize the settling response of the drive amplifier. when choosing values of source resistance and shunt capacitance, the drive amplifier data sheet should be consulted and followed for optimum settling response. if lower input bandwidths are desired, care should be taken to optimize the settling response of the driver amplifier with higher values of shunt capacitance or series resistance. high quality capacitors and resistors should be used in the rc filter since these components can add distortion. np0/ c0g and silver mica type dielectric capacitors have excel - lent l inearity. carbon s urface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. when high amplitude unwanted signals are close in frequency to the desired signal frequency, a multiple pole filter is required. high external source resistance, combined with external shunt capacitance at pin 4 will significantly reduce the input bandwidth and may increase the required acquisi- tion time beyond the minimum acquisition time ( t acq-min ) of 700ns. figure 10. rc input filter 470pf 50 231214 f10 a in LTC2312-14 lt1818 gnd analog in + ? adc reference a low noise, low temperature drift reference is critical to achieving the full data sheet performance of the adc . the LTC2312-14 provides an excellent internal reference with a guaranteed 20ppm/ c maximum temperature coefficient. for added flexibility, an external reference may also be used. the high speed, low noise internal reference buffer is used only in the internal reference configuration. the reference 231214f ltc 2312-14
14 for more information www.linear.com/LTC2312-14 a pplica t ions i n f or m a t ion buffer must be overdriven in the external reference con- figuration with a voltage 50 mv higher than the nominal reference output voltage in the internal configuration. using the internal reference the internal bandgap and reference buffer are active by default when the LTC2312-14 is not in sleep mode. the reference voltage at the ref pin scales automatically with the supply voltage at the v dd pin. the scaling of the refer- ence voltage with supply is shown in table 2. table 2. reference voltage vs supply range supply voltage (v dd ) ref voltage (v ref ) 2.7v < v dd < 3.6v 2.048v 4.75v < v dd < 5.25v 4.096v the reference voltage also determines the full-scale analog input range of the LTC2312-14. for example, a 2.048 v reference voltage will accommodate an analog input range from 0 v to 2.048 v . an analog input voltage that goes below 0v will be coded as all zeros and an analog input voltage that exceeds 2.048v will be coded as all ones. it is recommended that the ref pin be bypassed to ground with a low esr , 2.2 f ceramic chip capacitor for optimum performance. external reference an external reference can be used with the LTC2312-14 if better performance is required or to accommodate a larger input voltage span. the only constraints are that the external reference voltage must be 50 mv higher than figure 11. LTC2312-14 transfer function figure 12. histogram for 16384 conversions the internal reference voltage ( see table 2) and must be less than or equal to the supply voltage (or 4.3 v for the 5v supply range). for example, a 3.3 v external reference may be used with a 3.3 v v dd supply voltage to provide a 3.3v analog input voltage span (i.e. 3.3v > 2.048v + 50 mv). or alternatively, a 2.5 v reference may be used with a 3v supply voltage to provide a 2.5 v input voltage range (i.e. 2.5v > 2.048v + 50 mv). the ltc6655-3.3, ltc6655-2.5, available from linear technology, may be suitable for many applications requiring a high performance external reference for either 3.3 v or 2.5 v input spans respectively. transfer function figure 11 depicts the transfer function of the LTC2312-14. the code transitions occur midway between successive integer lsb values (i.e. 0.5lsb, 1.5lsb, 2.5 lsb fs- 0.5lsb). the output code is straight binary with 1lsb = v ref /16,384. dc performance the noise of an adc can be evaluated in two ways: signal-to-noise ratio ( snr) in the frequency domain and histogram in the time domain. the LTC2312-14 excels in both. the noise in the time domain histogram is the transition noise associated with a 14- bit resolution adc which can be measured with a fixed dc signal applied to the input of the adc. the resulting output codes are collected over a large number of conversions. the shape of the distribution of codes will give an indication of the magnitude of the transition noise. in figure 12, the distri - bution of output codes is shown for a dc input that has input voltage (v) output code 231214 f11 111...111 111...110 000...000 000...001 fs ? 1lsb 0 1lsb 231214 f12 code 8194 counts 8196 8197 8195 8198 8199 8200 = 0.7 0 2000 1000 3000 4000 5000 7000 6000 231214f ltc 2312-14
15 for more information www.linear.com/LTC2312-14 a pplica t ions i n f or m a t ion at the maximum sampling rate of 500 khz, the LTC2312-14 maintains an enob above 12 bits up to an input frequency of 1.25mhz. (figure 14) signal-to-noise ratio (snr) the signal- to- noise ratio ( snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency compon- ents except the first five harmonics and dc. figure 13 shows that the LTC2312-14 achieves a typical snr of 77.5db at a 500 khz sampling rate with a 259 khz input frequency. total harmonic distortion (thd) total harmonic distortion ( thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency (f smpl /2). thd is expressed as: thd = 20log v2 2 + v3 2 + v4 2 + v n 2 v1 where v1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. thd versus input frequency is shown in the typical performance characteristics section. the LTC2312-14 has excellent distortion performance well beyond the nyquist frequency. been digitized 16,384 times. the distribution is gaussian and the rms code transition noise is 0.7 lsb. this cor - responds to a noise level of 77.5 db relative to a full scale voltage of 4.096v. dynamic performance the LTC2312-14 has excellent high speed sampling capability. fast fourier transform ( fft ) techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequencies outside the applied fundamental. the LTC2312-14 provides guaranteed tested limits for both ac distortion and noise measurements. signal-to-noise and distortion ratio (sinad) the signal - to - noise and distortion ratio ( sinad) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the a/d output. the output is band- limited to frequencies from above dc and below half the sampling frequency. figure 14 shows the LTC2312-14 maintains a sinad above 76db up to an input frequency of 1.25mhz. effective number of bits (enob) the effective number of bits ( enob) is a measurement of the resolution of an adc and is directly related to sinad by the equation where enob is the effective number of bits of resolution and sinad is expressed in db: enob = (sinad C 1.76)/6.02 figure 13. 16k point fft of the LTC2312-14 at f in = 259khz figure 14. LTC2312-14 enob/sinad vs f in 231214 f13 input frequency (khz) amplitude (dbfs) 0 200 250 10050 150 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 v dd = 5v snr = 77.5dbfs sinad = 77dbfs thd = ?85db sfdr = 88db 231214 f14 input frequency (khz) sinad (dbfs) enob 0 1250 750 500 250 1000 78 77 76 75 74 73 72 71 12.50 12.33 12.17 12.00 11.83 11.67 11.50 v dd = 5v v dd = 3v 231214f ltc 2312-14
16 for more information www.linear.com/LTC2312-14 a pplica t ions i n f or m a t ion intermodulation distortion (imd) if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion ( imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies f a and f b are ap- plied to the adc input, nonlinearities in the adc transfer function can create distortion products at the sum and difference frequencies m ? f a n ? f b , where m and n = 0, 1, 2, 3, etc. for example, the 2 nd order imd terms include (f a f b ). if the two input sine waves are equal in magnitude, the value ( in decibels) of the 2 nd order imd products can be expressed by the following formula: imd(f a f b ) = 20 ? log[v a (f a f b )/v a (f a )] the LTC2312-14 has excellent imd, as shown in figure 15. figure 15. LTC2312-14 imd plot 231214 f15 input frequency (khz) magnitude (db) 0 250 10050 150 200 0 ?20 f a f b 2f a ? f b 2f b ? f a f b ? f a ?40 ?60 ?80 ?100 ?120 ?140 ?160 v dd = 5v f s = 500ksps f a = 53.421khz f b = 58.421khz imd 2 (f b ? f a ) = ?80.4dbc imd 3 (2f b ? f a ) = ?92dbc f b + f a spurious free dynamic range (sfdr) the spurious free dynamic range is the largest spectral component excluding dc and the input signal. this value is expressed in decibels relative to the rms value of a full-scale input signal. full-power and C3db input linear bandwidth the full-power bandwidth is the input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input signal. the C3 db linear bandwidth is the input frequency at which the sinad has dropped to 74db (12 effective bits). the LTC2312-14 has been designed to optimize the input bandwidth, allowing the adc to under- sample input signals with frequencies above the converters nyquist frequency. the noise floor stays very low at high frequencies and sinad becomes dominated by distortion at frequencies beyond nyquist. recommended layout to obtain the best performance from the LTC2312-14 a printed circuit board is required. layout for the printed circuit board ( pcb) should ensure the digital and analog signal lines are separated as much as possible . in particu - lar, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the adc. figure 16 through figure 20 is an example of a recom- mended pcb layout. a single solid ground plane is used. bypass capacitors to the supplies are placed as close as possible to the supply pins. low impedance common returns for these bypass capacitors are essential to the low noise operation of the adc. the analog input traces are screened by ground. for more details and information refer to dc1563, the evaluation kit for the LTC2312-14. bypassing considerations high quality tantalum and ceramic bypass capacitors should be used at the v dd , ov dd and ref pins. for opti- mum per formance, a 2.2 f ceramic chip capacitor should be used for the v dd and ov dd pins. the recommended bypassing for the ref pin is also a low esr , 2.2 f ceramic capacitor. the traces connecting the pins and the bypass capacitors must be kept as short as possible and should be made as wide as possible avoiding the use of vias. all analog circuitry grounds should be terminated at the LTC2312-14. the ground return from the LTC2312-14 to the power supply should be low impedance for noise free operation. digital circuitry grounds must be connected to the digital supply common. 231214f ltc 2312-14
17 for more information www.linear.com/LTC2312-14 a pplica t ions i n f or m a t ion figure 16. top silkscreen figure 17. layer 1 top layer figure 18. layer 2 gnd plane in applications where the adc data outputs and control signals are connected to a continuously active micropro- cessor bus , it is possible to get errors in the conversion results. these errors are due to feed-through from the microprocessor to the successive approximation com- parator. the problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to isolate the adc data bus. 231214f ltc 2312-14
18 for more information www.linear.com/LTC2312-14 figure 19. layer 3 pwr plane figure 20. layer 4 bottom layer figure 21. partial 1563 demo board schematic a pplica t ions i n f or m a t ion 4 9v to 10v u5 lt1790acs6-2.048 1 1 ac j4 dc coupling 2 3 2 6 gnd gnd v dd ref csl sck sdo sdo ov dd vi vo vcm v dd vccio c8 10f c9 4.7f c10 opt c11 opt c12 4.7f c7 opt ref + c6 4.7f r9 1k c18 opt r18 1k 3 1.024v 2.048v hd1x3-100 2 1 c17 1f jp2 v cm r14 0k r15 49.9 r16 33 4 3 231214 f21 1 2 5 8 7 6 u1 * c19 47pf np0 jp1 hd1x3-100 a in 0v to 4.096v a in gnd csl* *note: csl = conv sck 231214f ltc 2312-14
19 for more information www.linear.com/LTC2312-14 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 1.50 ? 1.75 (note 4) 2.80 bsc 0.22 ? 0.36 8 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) ts8 tsot-23 0710 rev a 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.40 max 0.65 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref ts8 package 8-lead plastic tsot-23 (reference ltc dwg # 05-08-1637 rev a) 231214f ltc 2312-14
20 for more information www.linear.com/LTC2312-14 ? linear technology corporation 2013 lt 0913 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LTC2312-14 r ela t e d p ar t s typical a pplica t ion low jitter clock timing with rf sine generator using clock squaring/level-shifting circuit and re-timing flip-flop part number description comments adcs ltc2314-14 14-bit, 4.5msps serial adc 3v/5v, 18mw/31mw, 20ppm/c max internal reference, single- ended, 8-lead tsot-23 package ltc2313-14 14-bit, 2.5msps serial adc 3v/5v, 14mw/25mw, 20ppm/c max internal reference, single-ended input, 8-lead tsot-23 package l t c1403 a/ ltc1403 a -1 14-bit, 2.8msps serial adc 3v, 14mw, unipolar/bipolar inputs, msop package ltc1407 a/ ltc1407 a -1 14-bit, 3msps simultaneous sampling adc 3v, 2-channel differential, unipolar/bipolar inputs, 14mw, msop package l t c2355 / ltc2356 12-/14-bit, 3.5msps serial adc 3.3v supply, differential inputs, 18mw, msop package ltc2365 / ltc2366 12-bit, 1msps/3msps serial sampling adc 3.3v supply, single-ended, 8mw, tsot-23 package amplifiers lt6200 / lt6201 single/dual operational amplifiers 165mhz, 0.95nv/hz lt6230 / lt6231 single/dual operational amplifiers 215mhz, 3.5ma/amplifier, 1.1nv/hz lt6236 / lt6237 single/dual operational amplifier with low wideband noise 215 mhz, 3.5ma/amplifier, 1.1nv/ hz lt1818 / lt1819 single/dual operational amplifiers 400mhz, 9ma/amplifier, 6nv/hz references ltc6655-2.5/ltc6655-3.3 precision low drift low noise buffered reference 2.5v/3.3v, 5ppm/c, 0.25ppm peak-to-peak noise, msop-8 package l t 1461-3/lt1461-3.3 v precision series voltage family 0.05% initial accuracy, 3ppm drift control logic (fpga, cpld, dsp, etc.) 50 1k 1k 0.1f v cc v cc nc7svu04p5x nl17sz74 nc7svuo4p5x master clock sdo enable d pre clr conv q conv sck sdo > LTC2312-14 33 231214 ta02 231214f ltc 2312-14

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